Process for producing semiconductor integrated circuit device

ABSTRACT

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

TECHNICAL FIELD

[0001] This invention relates to a fabrication technology of asemiconductor integrated circuit device. More particularly, thisinvention relates to a technology which will be effective when appliedto a “Salicide” (self-aligned silicide) process using a Co (cobalt) filmformed by sputtering.

BACKGROUND OF THE INVENTION

[0002] Polycrystalline silicon and Al (aluminum) have been used mainlyin the past as electrode and wiring materials of semiconductorintegrated circuits formed on a Si (silicon) substrate. As semiconductordevices have been scaled down in recent years, however, attempts havebeen made to introduce refractory metals such as W (tungsten), Ti(titanium), cobalt, etc, and their silicide compounds, as new electrodeand wiring materials because these metals and metal compounds have lowerresistance than Si and higher electromigration resistance than Al.

[0003] The refractory metal (silicide) film for these electrode andwiring materials is formed on a semiconductor wafer by sputtering inargon a target that is prepared by sintering powder of the refractorymetal (silicide).

[0004] Japanese Patent Laid-Open Nos. 192974/1994, 192979/1994 and3486/1995 disclose a technology for producing high purity Co whichreduces its impurity contents, particularly the Ni (nickel) and Fe(iron) contents, and has a purity of over 99.999% (5N), by anelectrolytic refining process. This high purity Co is applied to theproduction of a Co target for forming a Co film used for the electrodesand wiring lines (electrodes, gates, wiring lines, devices, protectivefilms, etc.) of semiconductor devices.

[0005] Japanese Patent Laid-Open No. 1370/1993 describes a method ofproducing a refractory metal silicide target for sputtering, capable ofrestricting the formation of particles that would otherwise result inbreakage and short-circuit of the electrodes and wiring lines. Thisreference illustrates W, Mo (molybdenum), Ta (tantalum), Ti, Co and Cr(chromium) as the refractory metals.

[0006] The refractory metal silicide film can be formed by a refractorymetal film to react with silicon, besides the method described abovethat uses the target of the refractory metal silicide.

[0007] Japanese Patent Laid-Open No. 321069/1995 describes a so-called“Salicide process” which comprises the steps of forming a Co-Ti film onthe entire surface of a semiconductor substrate, on which MOSFETs (MetalOxide Semiconductor Field Effect transistors) are formed, by a magnetronsputtering process using a composite metal target constituted by 20 atom% of a ferromagnetic material such as Co and 80 atom % of a paramagneticmaterial such as Ti, then conducting heat-treatment so as to form a Cosilicide-Ti silicide mixture layer on the polycrystalline silicon gatesas well as on the sources and drains, removing unreacted potions of themixture layer by etching, and conducting again the heat-treatment tothereby reduce the resistance of the mixture layer.

DISCLOSURE OF THE INVENTION

[0008] In order to achieve high operation speed, high performance andlow power consumption of large-scale semiconductor devices using verysmall MOSFETs fabricated by a deep sub-micron design rule of not greaterthan 0.25 μm, for example, it is essentially necessary to materializethe high-speed operation of discrete MOSFETs in addition to thereduction of the delay in wiring lines. For, the source/drain resistanceof the MOSFET increases when the MOSFET is scaled down, and thisincrease in the resistance is a critical factor that impedes thehigh-speed operation of the transistors. In the case of low powerconsumption devices for driving the transistors at a low voltage of 2 Vor below, in particular, the improvement of the operation speed of thediscrete MOSFET is the critical problem.

[0009] When the MOSFET is driven at a low voltage of 2 V or below, itbecomes difficult to control a threshold voltage (Vth) in a buriedchannel type structure, in which the gate electrode is constituted by ntype polycrystalline silicon, as is the case with p channel MOSFETs ofthe prior art. Therefore, how to control the threshold voltage isanother problem.

[0010] The inventors of the present invention have examined theintroduction of the Salicide process for forming a low-resistance highmelting silicide layer on the polycrystalline silicon gates and on bothsource and drain so as to solve the problem of the high-speed operationof the MOSFET. The inventors have selected Co (cobalt) that provides alow resistance silicide of about 15 μΩcm as a refractory metal material.To control the threshold voltage of the MOSFET, on the other hand, theinventors have attempted to introduce a dual-gate CMOS structure inwhich the gate electrode of p channel MOSFETs is constituted into asurface channel type by p type polycrystalline silicon while the gateelectrode of n channel MOSFETs is constituted into the surface channeltype by n type polycrystalline silicon. To introduce this dual-gate CMOSstructure, the connection method of the p type polycrystalline silicongate and the n type polycrystalline silicon gate becomes the problem,but this problem can be solved by combining this structure with theSalicide process for forming the silicide layer on the polycrystallinesilicon gates.

[0011] The process for forming the Co silicide layer on thepolycrystalline silicon gates and on the source and drain of the MOSFETis as follows.

[0012] First, a Co film is deposited on a semiconductor substrate havingMOSFETs formed thereon, by a sputtering process using a Co target, andheat-treatment is then effected so as to permit Co and Si to react witheach other and to thereby form a Co silicide layer on the surface ofeach of the gate, source and drain (first heat-treatment). The Cosilicide obtained at this time is a mono-silicide (CoSi) having arelatively high resistance of 50 to 60 μΩcm. After the unreacted Co filmis removed by wet etching, heat-treatment is carried out once again tocause the phase transition of the mono-silicide to a di-silicide (CoSi₂)having a low resistance (second heat-treatment).

[0013] When the present inventors have carried out the firstheat-treatment for the Co film formed by using Co target having a purityof 99.9%, however, the film thickness of the resulting Co mono-silicide(CoSi) exhibits high dependence on the temperature change of theheat-treatment. More concretely, the phenomenon is observed in which thefilm thickness becomes greater with a higher heat-treatment temperatureand smaller with a lower heat-treatment temperature. Consequently, thefilm thickness cannot be controlled stably. Presumably, such a variationof the film thickness results mainly from silicidization of a part ofimpurity transition metals such as Fe and Ni contained in the Co target.

[0014] The result of the studies described above suggests that in orderto obtain a Co silicide layer having a low resistance, the filmthickness of the mono-silicide layer must be made sufficiently large bysetting the temperature of the first heat-treatment to a high level.When the film thickness of the mono-silicide layer becomes large,however, a junction leakage current increases in 0.25 μm MOS devices inwhich the source-drain p-n junction is shallower than 0.3 μm. It isassumed that excessive inter-lattice Si formed by the reaction betweenCo, which enters the substrate, and Si, gathers and grows to therebyinvite this increase in the junction leakage current.

[0015] If the first heat-treatment temperature is raised, an undesirablesilicidization reaction is likely to occur at the source-drain endportion and to result in so-called “creep-up”, or the phenomenon inwhich the silicide layer extends up to the field insulating film and thegate side wall insulating film. As a result, short-circuit develops inMOSFETs of a very small size between the gate and the source, betweenthe gate and the drain and between the sources and the drains ofadjacent MOSFETs. When the first heat-treatment is applied to the dualgate CMOSs, in particular, B (boron) as the impurity in p typepolycrystalline silicon, that constitutes the gate electrode of the pchannel MOSFET, is likely to diffuse into the gate oxide film with theresult that electric characteristics of the transistors are likely tofluctuate.

[0016] On the other hand, when the film thickness of the mono-silicidelayer is reduced by setting the first heat-treatment temperature to alow level so as to avoid the increase in the junction leakage current,the resistance of the silicide layer increases. When the heat-treatmenttemperature is low, the progress of the silicidization reaction becomesslow, too, so that the resistance of the silicide layer furtherincreases. Furthermore, the heat resistance of the Co silicide layerdrops when its film thickness becomes small. In consequence,agglomeration of the crystal grains of the Co silicide occurs during theheat-treatment process after the formation of the MOSFET (e.g. theprocess in which a silicon oxide film containing P (phosphorus) dopedthereto is deposited on the MOSFET and is then sintered at a hightemperature in order to getter a metal such as Na (sodium)).Consequently, the abnormal increase in the resistance occurs.

[0017] Therefore, a method of fabricating a semiconductor integratedcircuit device according to the present invention comprises thefollowing steps (a) to (d):

[0018] (a) a step of forming MOSFETs on a main plane of a wafer;

[0019] (b) a step of depositing a Co film to regions of the main planeof the wafer including at least the upper portions of the gate electrodeand the source and drain of the MOSFET by sputtering using a high purityCo target;

[0020] (c) a step of forming a Co silicide layer on the surface of thegate electrode and the source and drain of each MOSFET by applying afirst heat-treatment to the wafer so as to allow Co and Si to react witheach other; and

[0021] (d) a step of removing the unreacted portions of the Co film andthen applying a second heat-treatment to the wafer so as to reduce theresistance of the Co silicide layer.

[0022] When the CoSi₂ layer is formed on the silicon surface by thereaction of Co with Si, the fabrication method of the semiconductorintegrated circuit device according to the present invention reduces thesheet resistance of the CoSi₂ layer to 10 Ω/square or below by using thehigh impurity Co target capable of providing the CoSi layer that has lowtemperature dependence on at least the first heat-treatment temperatureand has improved film thickness controllability.

[0023] The high purity Co target used in the present invention has a Copurity of at least 99.99% and a Fe or Ni content of not greater than 10ppm, or the sum of the Fe and Ni contents of not greater than 50 ppm.Preferably, the Co purity is at least 99.99% and the Fe and Ni contentsare not greater than 10 ppm and more preferably, the Co purity is99.999%.

[0024] The term “wafer” used in this specification means a sheet-likearticle at least a part of which comprises a single, or a plurality of,single crystal regions (mainly silicon in the invention) after at leastprescribed process steps that form the semiconductor integrated circuitdevice mainly on the main surface region thereof. The term“semiconductor integrated circuit device” used herein means not onlythose which are formed on ordinary single crystal wafers but on othersubstrates, such as TFT liquid crystals.

[0025] The summary of the inventions disclosed herein can be itemized asfollows.

[0026] (1) A method of fabricating a semiconductor integrated circuitdevice comprising the steps of:

[0027] (a) forming MOSFETs on a main plane of a wafer;

[0028] (b) depositing a Co film in regions of the main plane of thewafer including at least the gate electrode and the source and drain ofeach MOSFET by sputtering using a high purity Co target;

[0029] a step of applying a first heat-treatment to the wafer so as toallow Co and Si to react with each other and to form a Co silicide layeron the surfaces of the gate electrode and the source and drain of eachMOSFET; and

[0030] (d) removing the unreacted portions of the Co film and applying asecond heat-treatment to the wafer so as to reduce the resistance of theCo silicide layer.

[0031] (2) According to the method of fabricating a semiconductorintegrated circuit device of the invention described above, the Copurity of the Co target is at least 99.99% and the Fe or Ni content isnot greater than 10 ppm.

[0032] (3) According to the method of fabricating a semiconductorintegrated circuit device described above, the Co purity of the Cotarget is at least 99.99% and the Fe and Ni contents are not greaterthan 50 ppm.

[0033] (4) According to the method of fabricating a semiconductorintegrated circuit device described above, the Co purity of the Cotarget is at least 99.99% and the Fe and Ni contents are not greaterthan 10 ppm.

[0034] (5) According to the method of fabricating a semiconductorintegrated circuit device described above, the Co purity of the Cotarget is 99.999%.

[0035] (6) According to the method of fabricating a semiconductorintegrated circuit device described above, the temperature of the firstheat-treatment is from 475 to 525° C.

[0036] (7) According to the method of fabricating a semiconductorintegrated circuit device described above, the temperature of the secondheat-treatment is from 650 to 800° C.

[0037] (8) According to the method of fabricating a semiconductorintegrated circuit device described above, the film thickness of the Cofilm is from 18 to 60 nm.

[0038] (9) According to the method of fabricating a semiconductorintegrated circuit device described above, the sheet resistance of theCo silicide layer after the application of the second heat-treatment isnot greater than 10 Ω/square.

[0039] (10) According to the method of fabricating a semiconductorintegrated circuit device described above, the junction depth of thesource and the drain is not greater than 0.3 μm.

[0040] (11) A method of fabricating a semiconductor integrated circuitdevice according to the present invention comprises the steps of:

[0041] (a) depositing a polycrystalline silicon film and a firstinsulating film on a main plane of a wafer having a gate insulating filmformed thereon, and patterning the first insulating film and thepolycrystalline silicon film to thereby form a first gate electrodepattern in a first region of the wafer and a second gate electrodepattern in a second region;

[0042] (b) implanting an impurity ion of a first conductivity type intothe first region of the wafer to form first conductivity typesemiconductor regions having a low impurity concentration in the waferon both sides of the first gate electrode pattern, and implanting animpurity ion of a second conductivity type into the second region of thewafer to form second conductivity type semiconductor regions in thewafer on both sides of the second gate electrode pattern;

[0043] (c) patterning the second insulating film deposited on the mainplane of the wafer to form side wall spacers on side walls of the firstand second gate electrodes, and removing the first insulating films ofthe first and second gate electrode patterns to expose the surface ofthe polycrystalline silicon film;

[0044] (d) implanting an impurity ion of the first conductivity typeinto the first region of the wafer to form a first gate electrode of thefirst conductivity type by the polycrystalline silicon film of the firstgate electrode pattern and to form first conductivity type semiconductorregions having a high impurity concentration in the wafer on both sidesof the first gate electrode, and implanting an impurity ion of thesecond conductivity type into the second region of the wafer to form asecond gate electrode of the second conductivity type by thepolycrystalline silicon film of the second gate electrode pattern, andto form second conductivity type semiconductor regions having a highimpurity concentration in the wafer on both sides of the second gateelectrode;

[0045] (e) depositing a Co film on the main plane of the wafer bysputtering using a high purity Co target;

[0046] (f) applying a first heat-treatment to the wafer to allow Co andSi to react with each other to thereby form a Co silicide layer on thesurface of the first and second gate electrodes and the surface of thefirst and second conductivity type semiconductor regions having a highimpurity concentration; and

[0047] (g) removing the unreacted portion of the Co film and thenapplying a second heat-treatment to the wafer to lower the resistance ofthe Co silicide layer.

[0048] (12) According to the method of fabricating a semiconductorintegrated circuit device of the present invention described above, anoperating power source voltage of the MOSFET is not higher than 2 V.

[0049] (13) According to the method of fabricating a semiconductorintegrated circuit device described above, the Co purity of the Cotarget is at least 99.99% and the Fe or Ni content is not greater than10 ppm.

[0050] (14) According to the method of fabricating a semiconductorintegrated circuit device described above, the Co purity of the Cotarget is at least 99.99% and the Fe and Ni contents are not greaterthan 50 ppm.

[0051] (15) According to the method of fabricating a semiconductorintegrated circuit device described above, the Co purity of the Cotarget is at least 99.99% and the Fe and Ni contents are not greaterthan 10 ppm.

[0052] (16) According to the method of fabricating a semiconductorintegrated circuit device described above, the Co purity of the Cotarget is 99.999%.

[0053] (17) A method of fabricating a semiconductor integrated circuitdevice according to the present invention comprising the steps of:

[0054] (a) forming MOSFETs on a main plane of a wafer and then exposingthe surface of the gate electrode and the source and drain of eachMOSFET;

[0055] (b) depositing a Co film on the main plane of the wafer includingthe surface of the gate electrode and the source and drain of the MOSFETby sputtering using a high purity Co target;

[0056] (c) applying a first heat-treatment to the wafer to allow Co andSi to react with each other to thereby form a Co silicide layer mademainly of Co mono-silicide on the surface of the gate electrode, thesource and drain of the MOSFET;

[0057] (d) removing the unreacted portions of the Co film and thenapplying a second heat-treatment to cause phase transition of the Cosilicide layer to a Co di-silicide layer made mainly of a Codi-silicide; and

[0058] (e) depositing a silicon oxide film containing an impurity dopedthereto to the upper part of the MOSFET so as to getter a metalimpurity, and then applying a third heat-treatment to the silicon oxidefilm.

[0059] (18) According to the method of fabricating a semiconductorintegrated circuit device of the invention described above, the siliconoxide film containing the impurity doped thereto is a PSG film.

[0060] (19) According to the method of fabricating a semiconductorintegrated circuit device described above, the temperature of the thirdheat-treatment is from 700 to 800° C.

[0061] It is an object of the present invention to provide a Salicideprocess capable of forming a Co silicide layer having a low resistanceand a small junction leakage current.

[0062] These and other objects and novel features of the presentinvention will become more apparent from the following description ofthe specification together with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0063] FIGS. 1 to 7, 9, 12, 13 and 16 to 20 are sectional views ofprincipal portions of a semiconductor substrate, and show methods offabricating a semiconductor integrated circuit device according toembodiments of the present invention.

[0064]FIG. 8 is a graph showing the relationship between heat-treatmentat 750° C. for 30 minutes for activating an impurity and a leakagecurrent of the source and drain formed of this impurity.

[0065]FIG. 10 is a schematic view of a chamber of a sputtering apparatusused for depositing a Co film.

[0066]FIG. 11 is a perspective view of a Co target.

[0067]FIG. 14 is an enlarged view of n- and p-channel MOSFETs eachhaving a Co silicide layer formed on the surface of the gate electrode,the source and drain.

[0068]FIG. 15 is a graph showing the relationship between the sheetresistance of the Co silicide layer and the first heat-treatmenttemperature.

BEST MODE FOR CARRYING OUT THE INVENTION

[0069] The present invention will be described in further detail withreference to the accompanying drawings. In the explanation that follows,the same reference numeral will be used to identify a constituentelement having the same function, and repetition of the explanation ofsuch an element will be omitted.

[0070] The embodiment represents the example of the application of thepresent invention to a dual gate CMOS process in accordance with a 0.25μm design rule, wherein an operating power source voltage is 2 V.Needless to say, however, the present invention is not limited to thisembodiment.

[0071] A CMOSFET having a dual gate structure is fabricated in thefollowing way. First, the surface of a semiconductor substrate 1 made ofa p⁻ type single crystal silicon and having a resistivity of about 10Ωcm is thermally oxidized so as to form a 10 nm-thick silicon oxide film2. A 100 nm-thick silicon nitride film 3 is then deposited on thissilicon oxide film 2 by a CVD process, as shown in FIG. 1. Next, thissilicon nitride film 3 is patterned by dry etching using a photoresistas a mask so as to remove the silicon nitride film 3 of a deviceisolation region.

[0072] Next, as shown in FIG. 2, the silicon oxide film 2 and thesemiconductor substrate 1 are etched by using the silicon nitride film 3as the mask in such a manner as to form a 350 nm-deep trench 4 a in thesemiconductor substrate 1 of the device isolation region.

[0073] After a silicon dioxide film 5 is deposited on the semiconductorsubstrate 1 by the CVD process as shown in FIG. 3, the surface of thissilicon oxide film 5 is polished flat and smooth by a CMP process insuch a manner as to leave the silicon oxide film 5 inside the trench 4 aand thus to form a device isolation trench 4. Subsequently,heat-treatment is carried out at 1,000° C. to densify the silicon oxidefilm 5 inside the device isolation trench 4 and then the silicon nitridefilm 3 is removed by wet etching using hot phosphoric acid.

[0074] An n type well 6 n and a p type well 6 p are then formed in thesemiconductor substrate 1 as shown in FIG. 4. First, an impurity forforming the n type well in the semiconductor substrate 1 ision-implanted using a photoresist having an opening corresponding to a pchannel MOSFET forming region as a mask, and then an impurity foradjusting the threshold voltage of the p channel MOSFET ision-implanted. The impurity for forming the n type well is P(phosphorus), for example, and ion implantation is executed at energy of360 keV and a dose of 1.5×10¹³/cm². The impurity for adjusting thethreshold voltage is P, for example, and ion implantation is executed atenergy of 40 keV and a dose of 2×10¹²/cm². After the photoresist isremoved, an impurity for forming the p type well in the semiconductorsubstrate 1 is ion-implanted using a photoresist, that has an openingcorresponding to an n channel MOSFET, as a mask, and an impurity ion foradjusting the threshold voltage of the n channel MOSFET is furtherion-implanted. The impurity for forming the p type well is B (boron),for example, and ion implantation is executed at energy of 200 keV and adose of 1.0×10¹³/cm². The impurity for adjusting the threshold voltageis boron fluoride (BF₂) and ion implantation is executed at energy of 40keV and a dose of 2×10¹²/cm². Thereafter, the semiconductor substrate 1is heat-treated at 950° C. for one minute to activate the impurities,thereby forming the n type well 6 n and the p type well 6 p.

[0075] Next, a 4 nm-thick gate oxide film 7 is formed by thermallyoxidizing the semiconductor substrate 1 on the surface of the activeregion of each of the n and p type wells 6 n and 6 p as shown in FIG. 5,and a 250 nm-thick polycrystalline silicon film 8 is deposited by theCVD process on the semiconductor substrate 1. Furthermore, a siliconoxide film 9 is deposited on the polycrystalline silicon film 8 by CVD.None of the n type impurity and the p type impurity are doped into thepolycrystalline silicon film 8.

[0076] As shown in FIG. 6, the silicon oxide film 9 and thepolycrystalline silicon film 8 are then etched by using the photoresistas the mask in such a manner as to form the gate electrode 8 n of the nchannel MOSFET on the p type well 6 p and the gate electrode 8 p of thep channel MOSFET on the n type well. These gate electrodes 8 n and 8 pare shaped to a gate length of 0.25 μm.

[0077] Next, a p type impurity (BF₂) is ion-implanted to the n type well6 n by using the photoresist and the gate electrode 8 p as the mask atenergy of 20 keV and a dose of 7.0×10¹³/cm², and an n type impurity(arsenic (As)) is ion-implanted to the p type well 6 p at energy of 20keV and a dose of 3.0×10¹⁴/cm² by using the photoresist and the gateelectrode 8 n as the mask. Subsequently, the semiconductor substrate 1is heat-treated at 1,000° C. for 10 seconds so as to activate theimpurities and to form a p⁻ semiconductor regions 10 in the n type wells6 n on both sides of the gate electrode 8 p and n⁻ semiconductor regions11 in the p type wells 6 p on both sides of the gate electrode 8 n.

[0078] Side wall spacers 12 having a film thickness of 0.1 μm in thegate length-wise direction are formed on the side walls of the gateelectrodes 8 n and 8 p as shown in FIG. 7. The side wall spacer 12 isformed by anisotropically etching the silicon oxide film deposited byCVD to the semiconductor substrate 1 by reactive etching. When thisetching is carried out, the silicon oxide film 9 on the gate electrodes8 n and 8 p, too, is etched simultaneously, and the surface of the gateelectrodes 8 n and 8 p is exposed.

[0079] A p type impurity (B) is then ion-implanted to the n type well 6n and the gate electrode 7 p by using the photoresist as the mask atenergy of 20 keV and a dose of 1.0×10¹⁴/cm², and the p type impurity (B)is again ion-implanted at energy of 5 keV and a dose of 2.0×10¹⁵/cm².Next, after an n type impurity (P) is ion-implanted by using thephotoresist as the mask to the p type well 6 p and the gate electrode 8n at energy of 40 keV and a dose of 2.0×10¹⁴/cm², an n type impurity(As) is ion-implanted at energy of 60 keV and a dose of 3.0×10¹⁵/cm².Subsequently, the semiconductor substrate 1 is heat-treated at 1,000° C.for 10 seconds so as to activate the impurities, to thereby form a p⁺semiconductor region 13 in the n type well 6 n and to convert theconductivity type of the gate electrode 8 p to the p type. Also, an n⁺semiconductor region 14 is formed in the p type well 6 p, and theconductivity type of the gate electrode 8 n is converted to the n type.The p⁺ semiconductor region 13 and the n⁺ semiconductor region 14 areformed into the junction depth of 0.2 to 0.1 μm.

[0080] Incidentally, the (n⁺/p) junction leak of the n⁺ semiconductorregion 14 can be reduced by heat-treating the semiconductor substrate 1at 750° C. for 30 minutes prior to the heat treatment (at 1,000° C. for10 seconds) for activating the n type impurity and the p type impuritydescribed above, as shown in FIG. 8. This is because the spot defectintroduced into the semiconductor substrate 1 at the time of ionimplantation is recovered by this heat-treatment. Though the p⁺semiconductor region 13, too, is expected to provide a similar effect inthis case, the impurity (B) of the p⁺ semiconductor region 13 has a highdiffusion rate and diffuses to a certain extent even by theheat-treatment at such a temperature. To prevent this diffusion, it ispossible to first conduct heat-treatment at 750° C. for 30 minutesimmediately after the ion-implantation for forming the n⁺ semiconductorregion 14 and then to conduct heat-treatment at 1,000° C. for 10 secondsafter the ion-implantation for forming the p⁺ semiconductor region 13.

[0081] After the gate oxide film 7 on the surface of the p⁺semiconductor region 13 and the n⁺ semiconductor region 14 is removed bywet etching using hydrofluoric acid (HF), a 15 nm-thick Co film 16 isdeposited on the semiconductor substrate 1 by sputtering using a Cotarget and furthermore, a 10 to 15 nm-thick oxidation preventing film 17is deposited on this Co film 16, as shown in FIG. 9. A TiN filmdeposited by sputtering, for example, is used for the oxidationpreventing film 17. The film thickness of the Co film 16 is preferablywithin the range of 18 to 60 nm. If the film thickness is not greaterthan 18 nm, it becomes difficult to lower the sheet resistance of the Cosilicide layer to 10 Ω/square or below and if it exceeds 60 nm, thesource-drain junction leakage current increases.

[0082]FIG. 10 is a schematic view of a chamber of a sputtering apparatusused for the deposition of the Co film 16 described above. This chamber100 can be evacuated, and an Ar gas is introduced into this chamber,which is kept at several mTorr at the time of the film formation. A Cotarget 103 held by a sputter electrode 102 is so disposed above a holder101 for holding the semiconductor substrate 1 (wafer) as to oppose thesemiconductor substrate 1. When a power source 104 connected to the Cotarget 103 is operated and constant discharge is started, a plasma 105is generated by a high negative voltage applied to the Co target in agap between the Co target 103 and the semiconductor substrate 1. Whenthe Ar ions accelerated from this plasma 105 towards Co target 103impinge against the surface of the Co target 103, the constituentmaterial (Co) of the target scatters in the molecular (atomic) level anda Co film 16 is deposited on the surface of the semiconductor substrate1.

[0083]FIG. 11 is a schematic view of the Co target 103 described above.The Co target 103 used in this embodiment has a Co purity of at least99.99% and a Fe or Ni content of not greater than 10 ppm, or the Fe andNi contents of not greater than 50 ppm. Preferably, the Co purity is atleast 99.99% and the Fe and Ni contents are not greater than 10 ppm andmore preferably, the Co purity is 99.999%. Such a high purity target 103is produced by hot-pressing raw material powder of Co, that is refinedby an electrolytic process, or the like, until the Co purity describedabove can be obtained, into a sinter and machining the sinter into adisk.

[0084] Next, first heat-treatment is carried out so as to allow Co andSi to react with each other as shown in FIG. 12 and to form a CoSi layer16 a on the surface of each of the p⁺ semiconductor region 13, the n⁺semiconductor region 14 and the gate-electrodes 8 n and 8 p. This firstheat-treatment is executed by using an RTA (Rapid Thermal Anneal)apparatus in a nitrogen atmosphere for about 30 seconds while thesubstrate temperature is kept at 525° C. or below. If the heat-treatingtemperature is too low, however, the progress of the silicidizationreaction is impeded; hence, the substrate temperature is preferably setto at least 475° C.

[0085] After the oxidation preventing film 17 and the unreacted Co film16 are removed by wet etching using an aqueous solution of NH₄OH+H₂O₂and then an aqueous solution of HCl+H₂O₂, second heat-treatment iscarried out so as to cause the phase transition of the CoSi layer 16 ato a CoSi₂ layer 16 b as shown in FIG. 13. The second heat-treatment isexecuted by using the RTA apparatus in a nitrogen atmosphere for aboutone minute while the substrate temperature is set to 650 to 800° C.

[0086]FIG. 14 is an enlarged view of the n channel MOSFET and the pchannel MOSFET each including the CoSi₂ layer 16 b formed on the surfaceof the gate electrode and the source and drain. FIG. 15 is a graphshowing the relationship between the sheet resistance of the CoSi₂ layer16 b and the first heat-treatment temperature. A high purity producthaving a Co purity of 99.998% (target B) and a low purity product havinga Co purity of 99.9% (target A) are used as the Co target. Table 1 showsthe kind of impurities contained in these targets A and B and theircontents. TABLE 1 (unit: wt ppm) element target A target B Fe 50 4 Ni250 6 Cu <10 <1 Al <10 <1 C <10 6 O 6 50 Na <1 <0.05 K <1 <0.05

[0087] As shown in the drawings, the CoSi₂ layer 16 b obtained from thehigh purity target B having a purity of 99.998% has low firstheat-treating temperature dependence of CoSi layer 16 a and becomesvirtually uniform at a temperature within the range of from 500 to 600°C. Therefore, a low sheet resistance of about 4 Ω/square can be obtainedthroughout this temperature range.

[0088] Therefore, even when the first heat-treatment temperature is setto a low temperature, a CoSi₂ layer having a low sheet resistance can beobtained. As the heat-treatment temperature is lowered, the rate of thesilicidization reaction becomes low and film thickness controllabilityby the heat-treatment time can be improved. Therefore, the filmthickness of the CoSi₂ layer 16 b can be set more easily to the range inwhich the junction leakage current does not increase. Further, as theheat-treatment temperature is lowered, creep-up of the CoSi₂ layer 16 bcan be prevented.

[0089] As to the CoSi₂ layer obtained from the target A having thepurity of 99.9%, on the other hand, the sheet resistance increasesremarkably when the heat-treatment temperature is low because the filmthickness of the Co film becomes small. To obtain the sheet resistanceequal to that of the CoSi₂ layer obtained from the high purity target B,the first heat-treatment temperature must be raised to 600° C.

[0090] When the CoSi₂ layer is formed on the surface of each of the gateelectrode and the source and drain of the MOSFET by silicidizing the Cofilm which is deposited by sputtering in the manner described above, theembodiment of the present invention using the high purity Co targethaving a Co purity of at least 99.99% and the Fe and Ni contents of notgreater than 10 ppm, preferably the high purity Co target having a Copurity of 99.999%, can provide the Co silicide layer 16 b having a lowresistance and a low junction leakage current. Therefore, thisembodiment can promote the high operation speed, high performance andlow power consumption of devices using very small MOSFETs having a gatelength of 0.25 μm.

[0091] Next, a 100 nm-thick silicon oxide film 18 is deposited to thesemiconductor substrate 1 by a normal pressure CVD process, and a 300 to500 nm-thick silicon oxide film 19 is further deposited by a plasma CVD.The silicon oxide film 19 is then polished by chemical mechanicalpolishing (CMP) and its surface is made flat and smooth. After a 200nm-thick PSG film 20 is deposited on the silicon oxide film 19 by a CVDprocess using monosilane+oxygen+phosphine as a source gas,heat-treatment (sintering) is carried out at a temperature within therange of 700 to 800° C. for removing the moisture in the PSG film 20.Because this embodiment can sufficiently secure the film thickness ofthe CoSi₂ layer 16 b, agglomeration of the CoSi₂ layer 16 b can berestricted even when sintering is carried out at a high temperature. Inconsequence, the increase in the sheet resistance of the CoSi₂ layer 16b can be prevented and the process margin can be improved.

[0092] As shown in FIG. 17, the PSG film 20 and the silicon oxide films18 and 19 are etched by using the photoresist as the mask so as to forma connection hole 21 on each of the p⁺ and n⁺ semiconductor regions 13and 14, and then a first layer wiring line 22 is formed on the PSG film20. To form this first layer wiring line 22, a first TiN film is thinlydeposited on the PSG film 20 by CVD, and after a W film is depositedthick on this TiN film, the W film is etched back in such a manner as toleave it inside the connection hole 21. After an Al film and a secondTiN film are deposited by sputtering on the first TiN film, the secondTiN film, the Al film and the first TiN film are patterned by using thephotoresist as the mask.

[0093] Next, a first interlayer insulating film 23 is formed on thefirst layer wiring line 22 as shown in FIG. 18. After the surface ofthis interlayer insulating film 23 is made flat and smooth by chemicalmechanical polishing, a connection hole 24 is formed in the firstinterlayer insulating film 23. Subsequently, a second layer wiring line25 is formed on the first interlayer insulating film 23, and iselectrically connected to the first layer wiring line 22. The firstinterlayer insulating film 23 comprises the silicon oxide film depositedby plasma CVD and the second layer wiring line 25 is made of the samematerial as that of the first layer wiring line 22.

[0094] A second interlayer insulating film 26 is then formed on thesecond layer wiring line 25 in the same way as above as shown in FIG.19. After the surface of this film 26 is made flat and smooth and aconnection hole 27 is formed, a third layer wiring line 28 is formed onthe second interlayer insulating film 26.

[0095] Thereafter, a third interlayer insulating film 29 is formed onthe third layer wiring line 25 as shown in FIG. 20. After the surface ofthis film 29 is made flat and smooth and a connection hole 30 is formed,a fourth layer wiring line 31 is formed on the third interlayerinsulating film 29, then a fourth interlayer insulating film 32 isformed on the fourth layer wiring line 31. After the surface of thisfilm 32 is made flat and smooth and a connection hole 33 is formed, afifth layer wiring line 34 is formed on the fourth interlayer insulatingfilm 32. In this way, the semiconductor integrated circuit device ofthis embodiment is virtually completed.

[0096] Although the invention completed by the present inventors hasthus been described concretely with reference to the embodimentsthereof, the present invention is not particularly limited to theseembodiments but can naturally be changed or modified in various wayswithout departing from the scope thereof.

[0097] For example, the fabrication of the present invention that usesthe high purity Co target can be applied to the case where only thesurface of the source and drain of the MOSFET is converted to the Cosilicide, too.

[0098] Industrial Applicability

[0099] As described above, the fabrication method of a semiconductorintegrated circuit device according to the present invention can improvefilm thickness controllability of the Co silicide layer and can obtain aCo silicide layer having a low resistance and a low junction leakagecurrent. Therefore, this fabrication method can be applied suitably to aSalicide process using the Co target.

1. A method of fabricating a semiconductor integrated circuit devicecomprising the steps of: (a) forming MOSFETs on a main plane of a wafer;(b) depositing a Co film in regions on the main plane of said wafer inregions thereof including at least an upper portion of a gate electrode,source and drain of each of said MOSFETs by sputtering using a highpurity Co target; (c) applying first heat-treatment to said wafer andallowing Co and Si to react with each other so as to form a Co silicidelayer on the surface of the gate electrode, source and drain of saidMOSFET; and (d) removing unreacted portions of said Co film and thenapplying second heat-treatment to said wafer so as to lower theresistance of said Co silicide layer.
 2. A method of fabricating asemiconductor integrated circuit device according to claim 1, whereinthe Co purity of said Co target is at least 99.99% and a Fe or Nicontent is not greater than 10 ppm.
 3. A method of fabricating asemiconductor integrated circuit device according to claim 1, whereinthe Co purity of said Co target is at least 99.99% and Fe and Nicontents are not greater than 50 ppm.
 4. A method of fabricating asemiconductor integrated circuit device according to claim 1, whereinthe Co purity of said Co target is at least 99.99% and Fe and Nicontents are not greater than 10 ppm.
 5. A method of fabricating asemiconductor integrated circuit device according to claim 1, whereinthe Co purity of said Co target is 99.999%.
 6. A method of fabricating asemiconductor integrated circuit device according to claim 1, whereinthe temperature of said first heat-treatment is from 475 to 525° C.
 7. Amethod of fabricating a semiconductor integrated circuit deviceaccording to claim 1, wherein the temperature of said secondheat-treatment is from 650 to 800° C.
 8. A method of fabricating asemiconductor integrated circuit device according to claim 1, whereinthe film thickness of said Co film is from 18 to 60 nm.
 9. A method offabricating a semiconductor integrated circuit device according to claim1, wherein the sheet resistance of said Co silicide layer after theapplication of said second heat-treatment is not greater than 10Ω/square.
 10. A method of fabricating a semiconductor integrated circuitdevice according to claim 1, wherein said source-drain junction depth isnot greater than 0.3 μm.
 11. A method of fabricating a semiconductorintegrated circuit device comprising the steps of: (a) depositing apolycrystalline silicon film and a first insulating film on a main planeof a wafer having a gate insulating film formed thereon, and patterningsaid first insulating film and said polycrystalline silicon film in sucha manner as to from a gate electrode pattern in a first region of saidwafer and a second gate electrode pattern in a second region of saidwafer; (b) ion-implanting an impurity of a first conductivity type intosaid first region of said wafer to form first conductivity typesemiconductor regions in said wafer on both sides of said first gateelectrode pattern, and ion-implanting an impurity of a secondconductivity type into said second region of said wafer to form secondconductivity type semiconductor regions on both sides of said secondgate electrode pattern; (c) patterning a second insulating filmdeposited on the main plane of said wafer in such a manner as to formside wall spacers on side walls of said first and second gate electrodepatterns, respectively, and removing said first insulating film of bothof said first and second gate electrode patterns in such a manner as toexpose the surface of said polycrystalline silicon film; (d)ion-implanting an impurity of the first conductivity type into saidfirst region of said wafer in such a manner as to form a first gateelectrode of the first conductivity type by said polycrystalline siliconfilm of said first gate electrode pattern and to form first conductivitytype semiconductor regions in said wafer on both sides of said firstgate electrode, and ion-implanting an impurity of the secondconductivity type into said second region of said wafer in such a mannerto form a second gate electrode of the second conductivity type by saidpolycrystalline silicon film of said second gate electrode pattern andto form semiconductor regions of the second conductivity type having ahigh impurity concentration in said wafer on both sides of said secondgate electrodes; (e) depositing a Co film on the main plane of saidwafer by sputtering using a high purity Co target; (f) applying firstheat-treatment to said wafer so as to allow Co and Si to react with eachother and to form a Co silicide layer on the surface of said first andsecond gate electrodes and on the surface of said first and secondconductivity type semiconductor regions having a high impurityconcentration; and (g) removing unreacted portions of said Co film andapplying second heat-treatment to said wafer so as to lower theresistance of said Co silicide layer.
 12. A method of fabricating asemiconductor integrated circuit device according to claim 11, whereinan operating power source voltage of said MOSFET is not higher than 2 V.13. A method of fabricating a semiconductor integrated circuit deviceaccording to claim 11, wherein the Co purity of said Co target is atleast 99.99% and a Fe or Ni content is not greater than 10 ppm.
 14. Amethod of fabricating a semiconductor integrated circuit deviceaccording to claim 11, wherein the Co purity of said Co target is atleast 99.99% and Fe and Ni contents are not greater than 50 ppm.
 15. Amethod of fabricating a semiconductor integrated circuit deviceaccording to claim 11, wherein the Co purity of said Co target is atleast 99.99% and Fe and Ni contents are not greater than 10 ppm.
 16. Amethod of fabricating a semiconductor integrated circuit deviceaccording to claim 11, wherein the Co purity of said Co target is99.999%.
 17. A method of fabricating a semiconductor integrated circuitdevice comprising the steps of: (a) forming MOSFETs on a main plane of awafer and then exposing the surface of the gate electrode, source anddrain of each of said MOSFETs; (b) depositing a Co film on the mainplane of said wafer including the surface of the gate electrode, sourceand drain of each said MOSFET by sputtering using a high purity Cotarget; (c) applying first heat-treatment to said wafer so as to allowCo and Si to react with each other and to form a Co silicide layerconsisting mainly of a Co mono-silicide on the surface of the gateelectrode, source and drain of each said MOSFET; (d) removing unreactedportions of said Co film and applying second heat-treatment so as tocause phase transition of said Co silicide layer to a Co silicide layerconsisting mainly of a Co di-silicide; and (e) depositing a siliconoxide film containing an impurity doped therein for gettering a metalimpurity at an upper portion of said MOSFET and then applying thirdheat-treatment to said silicon oxide film.
 18. A method of fabricating asemiconductor integrated circuit device according to claim 17, whereinsaid silicon oxide film containing said impurity doped therein is a PSGfilm.
 19. A method of fabricating a semiconductor integrated circuitdevice according to claim 17, wherein the temperature of said thirdheat-treatment is within the range of 700 to 800° C.